Signal list
From TriPU
This page lists all signals in the schematics and their meaning:
- SIGNAL = normal signal (L = not asserted, H = asserted)
- /SIGNAL = inverted signal (L = asserted, H = not asserted)
- ^SIGNAL = rising edge triggered signal
- vSIGNAL = falling edge triggered signal
Hier sind alle verwendeten Signale aufgeschlüsselt. Bedeutung:
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register file
| signal name | direction | meaning |
|---|---|---|
| REGADDR | in | register address (0..31) |
| REGDATA | in/out | register data |
| REGWINDOW | intern | number of current register window |
| REGMEMADDR | intern | "real" adress of register |
| REGOVER | out | register file is overflowing |
| REGRESET | in | reset register window to 0 (registers hold values!) |
| ^REGWNDUP | in | increment register window |
| ^REGWNDDOWN | in | decrement register window |
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ALU
| signal name | direction | meaning |
|---|---|---|
| DATA | in/out | ALU data |
| ^STORA | in | store data bus in register A |
| ^STORB | in | store data bus in register B |
| ^STORX | in | store ALU result in register X |
| /ENX | in | put register X on data bus |
| STORFLAGS | in | store ALU result flags in flag register |
| ZERO | out | zero flag (last operation's result was zero) |
| SIGN | out | sign flag (last operations MSB was 1) |
| CARRY | out | addition overflow |
| ALUFUNC | in | ALU function (s.b.) |
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ALU functions
| function number (ALUFUNC) | function |
|---|---|
| 0 | addition without carry |
| 1 | addition with carry |
| 2 | logical OR |
| 3 | logical AND |
| 4 | logical NOT (only operand A) |
| 5 | logical left shift (only operand A) |
| 6 | logical right shift (only operand A) |
| 7 | logical XOR |
